library verilog;
use verilog.vl_types.all;
entity registers is
    port(
        CLK             : in     vl_logic;
        WE              : in     vl_logic;
        F               : in     vl_logic_vector(15 downto 0);
        rd              : in     vl_logic_vector(1 downto 0);
        rs              : in     vl_logic_vector(1 downto 0);
        rt              : in     vl_logic_vector(1 downto 0);
        t1              : out    vl_logic;
        out1            : out    vl_logic_vector(15 downto 0);
        out2            : out    vl_logic_vector(15 downto 0)
    );
end registers;
